1. Field of the Invention
The present disclosure relates to a clock data recovery (CDR) circuit, method, an equalized signal analyzing circuit and method, especially to circuits and methods that perform CDR and analyze equalized signal of a signal equalizer based on peak values of an input signal.
2. Description of Related Art
Referring to FIGS. 1A and 1B, waveforms of sampling an input signal Din by a clock clk are illustrated. In FIGS. 1A and 1B, two sampling results for one input data of the input signal Din are generated according to the clock clk. Ideally, a center of each unit interval (UI, each corresponding to one input data) of the input signal Din is sampled on a rising edge of the clock clk, and an edge of each UI is sampled on a falling edge of the clock clk. As a result, relatively accurate sampling results can be obtained. Traditionally, an Alexander phase detector is used to determine whether the clock clk leads or lags the input signal Din. As shown in FIG. 1A, one rising edge of the clock clk samples data D<n> (n being positive) in an UI, but the following falling edge samples at the subsequent UI instead of the edge of the corresponding UI; therefore, the Alexander phase detector determines that the clock clk lags the input signal Din by performing logic operation and averaging via a low-pass filter. In this case, the phase of the clock clk must be advanced (i.e., shifted to the left of FIG. 1A). On the other hand, as shown in FIG. 1B, data D<n> is sampled on a rising edge of the clock clk, but the corresponding UI, instead of the edge thereof, is sampled on the following falling edge; therefore, the Alexander phase detector determines that the clock clk leads the input signal Din. In this case, the phase of the clock clk must be delayed (i.e., shifted to the right of FIG. 1B). Reference is made to FIG. 2, a relationship between an eye diagram of input data and the clock clk is presented. After phase shift, the clock clk and the input signal Din achieve an ideal phase relationship. In other words, a center of each UI of the input signal Din is sampled on a rising edge of the clock clk, while an edge of each UI of the input signal Din is sampled on a falling edge. Ideally, the sampled data generated in such case are relatively accurate. However, the waveform of the input signal Din received by the sampling circuit is not symmetric most of the time because of interferences at a data receiving end. A peak value within a UI is not at the center of the UI, and therefore the rising edges of the clock clk do not ideally sample at the positions of the peak values of the input signal Din. For example, as shown in FIG. 2, the peak value of each input data is on the right half of the UI (depicted by a dotted circle). As a result, even if the clock clk samples at the center of each UI, it does not ideally sample at the positions of the peak values of the input signal Din, which may decrease the sampling accuracy and increase bit error rate (BER).
Referring to FIG. 3, a diagram of determining a position of a peak value of the input signal Din is presented. Two sampling points, which are advanced and delayed by a time Tb with respect to the normal sampling point (having a sampling result h(τ)), respectively correspond to the sampling results h(τ−Tb) and h(τ+Tb), in which Tb is half of time between the two successive sampling points. By comparing the two sampling results, the relationship between the sampling clock and the input signal Din can be determined. If h(τ−Tb)=h(τ+Tb), the sampling points of the sampling clock are aligned with the positions of the peak values of the input signal Din; if h(τ−Tb)>h(τ+Tb), the sampling clock lags the input signal Din, and therefore the sampling clock must be advanced to sample at the positions of peak values of the input signal Din; if h(τ−Tb)<h(τ+Tb), the sampling clock leads the input signal Din, and therefore the sampling clock must be delayed to sample at the positions of peak values of the input signal Din. Each data in this type of design requires more amplitude information; for example, 2 bits (4 levels) or even 4 bits are usually required, which results in larger circuit area, higher circuit complexity and more power consumption. Moreover, when the input signal Din presents asymmetric waveforms due to interferences, this design has difficulty finding the position of the peak value, which results in an increase in bit error rate.